The present invention relates to a process for manufacturing a semiconductor integrated circuit device having a ferroelectric (high relative dielectric constant substance) capacitor and, more particularly, to a technique which is effective when applied to a process for manufacturing a ferroelectric (high relative dielectric constant substance) capacitor by using a conductive material for producing reaction products of low vapor pressure at a dry-etching time.
In order to compensate the reduction in the amount of stored charge with the miniaturization of the memory cell of a large capacity DRAM (Dynamic Random Access Memory) exceeding 256 Mbits or 1 Gbits, it is demanded that the capacitor insulating film of a data storing capacitive element (or capacitor) is made of a high relative dielectric material having a specific relative dielectric constant of 20 or more such as Ta2O5 or BST ((Ba,Sr)TiO3), or a ferroelectric material having a relative dielectric constant over 100 such as PZT (PbZrxTi1xe2x88x92xO3), PLT (PbLaxTi1xe2x88x92xO3), PLZT, PbTiO3, SrTiO3 or BaTiO3.
In the field of a nonvolatile memory, there has been developed a ferroelectric memory which utilizes the polarization inversion of the ferroelectric material for data storage.
When the capacitor insulating film of the capacitor is made of an aforementioned ferroelectric substance (high relative dielectric constant substance), it is necessary to make the conductive films for electrodes sandwiching the capacitor insulating film, of such a refractory metallic material, e.g., Pt having a high affinity with those materials.
When the capacitor is made of Pt or PZT, there arises the following problem. When the thin film of Pt or PZT deposited on the substrate is dry-etched, it is known that a lot of reaction products having a low vapor pressure are deposited on the side face of a pattern to cause the short-circuiting between the capacitors.
In order to prevent reaction products from being deposited on the side face of the pattern when the Pt film is to be dry-etched, there is known in the prior art either a method of tapering the side face of a photoresist used as the etching mask or a method of using a hard mask of a silicon oxide film or a metal film in place of the photoresist.
It has been reported in 27p-N-9, Preprint No. 2 of the 43rd Joint Congress of Applied Physics of Japan 1996, that a clean capacitor without any side wall deposited film can be formed by using a resist mask having a side face tapered at about 75 degrees when a three-layered film of Pt/PZT/Pt deposited on a substrate is dry-etched. This can be thought in the following manner. If the side face of the resist mask is tapered, the side face of the pattern is also irradiated with etching ions so that the etch-off rate is enabled to exceed the deposition rate of the side wall deposited film by increasing the taper angle over a predetermined value (e.g., about 75 degrees).
It has been reported in 26a-ZT-4, Preprint No. 2 of 56th Joint Congress of Applied Physics of Japan 1995, that the Pt film can be tapered to effect the etching without any side wall deposited film, when the Pt film is dry-etched, by using as the mask a silicon oxide film etched to a predetermined pattern and by using an etching gas containing Ar and additional oxygen.
Japanese Patent Laid-Open No. 89662/1993 has disclosed a method of forming an excellent Pt pattern having no side wall deposited film by using as the mask a Ti film etched to a predetermined pattern thereby to etch the Pt film.
The RIE etching technique using a tapered resist mask has been disclosed on pp. 244 to 253, xe2x80x9cGlow Discharge Processes SPUTTERING AND PLASMA ETCHINGxe2x80x9d, by Brian Chapman.
According to our investigations, however, the prior art method of patterning the Pt film by using the resist mask having the tapered side face has problems of not only a complicated step of tapering the side face of the resist mask but also a difficulty in forming a fine Pt pattern in a high sizing accuracy.
On the other hand, the method of using the hard mask of the silicon oxide film or the metallic film forms a hard mask pattern by dry-etching such a film deposited on the Pt film, and has a problem of an increase in the steps, compared to the case of using the resist mask. During the etching, moreover, the hard mask has to be heated to as high as 300xc2x0 C. to raise other problems that when the Pt film over the ferroelectric (high relative dielectric constant substance) film is etched, the underlying ferroelectric (high relative dielectric constant substance) film is deteriorated, and that the hard mask is difficult to ash off after the end of the etching.
An object of the present invention is to provide a technique which can form a fine pattern, when a thin film of Pt or the like deposited on a substrate is patterned by a dry-etching method using a resist mask, without leaving reaction products of low vapor pressure on the side face of the pattern and in a high dimensional accuracy.
The aforementioned and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
The summaries of the invention will be briefly described in the following.
(1) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising the step of patterning by a dry-etching method a thin film, which has one or a plurality of films including a film formed directly or indirectly over a first major surface of a wafer and liable to be deposited on a side wall, by using as the mask a photoresist film of a predetermined pattern, which has a generally vertical side face of at least its lower half and which is either normally tapered or rounded at the outer periphery of its head, so that the side face of the thin film pattern may be normally tapered so as to reach the lower end thereof.
(2) The thin film pattern is overetched, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(3) The thin film includes a platinum thin film.
(4) The thin film includes a high relative dielectric constant thin film or a ferroelectric thin film.
(5) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a thin film, which has one or a plurality of films including a film liable to be deposited on a side wall, directly or indirectly over a first major surface of a wafer;
(b) the step of forming a photoresist of a predetermined pattern, which has a generally vertical side face of at least its lower half and which is either normally tapered or rounded at the outer periphery of its head, directly or indirectly over the thin film; and
(c) the step of patterning by a dry-etching method the thin film by using as the mask the photoresist film of the predetermined pattern so that the side face of the thin film pattern may be normally tapered so as to reach the lower end thereof.
(6) The thin film pattern is overetched, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(7) The thin film includes a platinum thin film.
(8) The thin film includes a high relative dielectric constant thin film or a ferroelectric thin film.
(9) According to the present invention, there is provided a semiconductor integrated circuit device manufacturing process, comprising:
(a) the step of forming a thin film, which has one or a plurality of films including a film liable to be deposited on a side wall, directly or indirectly over a first major surface of a wafer;
(b) the step of forming a positive type benzophenone novolak resist film by spin-coating over the thin film;
(c) the step of forming a predetermined resist film pattern by exposing and developing the positive type benzophenone novolak resist film;
(d) the step of setting the resist film pattern by heating at least the resist film pattern and by irradiating the surface of the same with ultraviolet radiation;
(e) the step of patterning by a dry-etching method the thin film by using as the mask the set photoresist film pattern so that the side face of the thin film pattern may be normally tapered so as to reach the lower end thereof; and
(f) overetching the thin film pattern, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern,
wherein at the end of the step (d), the surface insolubilization of the unexposed portion is weakened at the developing time of the positive type benzophenone novolak resist film so that the outer periphery of the head of the resist film pattern may be rounded.
(10) The thin film includes a platinum thin film.
(11) The thin film includes a high-dielectric thin film or a ferroelectric thin film.
(12) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device by repeating a photolithography processing by a reduction projection exposure using a positive or negative type photoresist and an exposure light of substantially the same wavelengths, to pattern a plurality of thin films, wherein a first photoresist of the positive or negative type is used at a portion of the step for the photolithography processing whereas a second photoresist having the same positive or negative type as that of the first photoresist but a different pattern shape and characteristic is used at the other portion of the step or at all the other steps.
(13) The first photoresist is a positive type benzophenone novolak resist whereas the second photoresist is a positive type non-benzophenone novolak resist.
(14) The semiconductor integrated circuit device manufacturing process of the present invention comprises the step of patterning the thin film having one or a plurality of films including a film liable to be deposited on the side wall, by using as the mask a resist pattern made of the first photoresist.
(15) The semiconductor integrated circuit device manufacturing process of the present invention comprises the step of overetching the thin film pattern, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(16) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a first thin film having one or a plurality of films directly or indirectly over a first major surface of a wafer;
(b) the step of forming a first photoresist film made of a positive type benzophenone novolak resist directly or indirectly over the first thin film;
(c) the step of forming a first resist film pattern over the first thin film by exposing the first photoresist film by a reduction projection exposure processing and subsequently by developing the exposed first photoresist film;
(d) the step of forming a gate electrode of a MISFET over the first major surface of the wafer by patterning the first thin film by a dry-etching method using as the mask the first resist film;
(e) the step of forming a second thin film having one or a plurality of films including a film, which is liable to be deposited on the side wall at the dry-etching time, directly or indirectly over the first major surface of the wafer formed with the gate electrode;
(f) the step of forming a second photoresist film made of a positive type benzophenone novolak resist by spin-coating over the second thin film;
(g) the step of forming a second resist film pattern over the second thin film by exposing the second photoresist film by a reduction projection exposure processing and subsequently by developing the exposed second photoresist film;
(h) the step of patterning the second thin film by a dry-etching method using as the mask the second resist film so that the side face of the thin film pattern may be normally tapered as to reach the lower end thereof; and
(i) overetching the thin film pattern, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(17) The second thin film is a thin film forming a capacitor of the memory cell of a DRAM.
(18) The second thin film is a thin film forming a capacitor of the memory cell of a ferroelectric RAM.
(19) The second thin film includes a thin film made of one or more metals or conductive metal oxides selected from the group consisting of Pt, Ir, IrO2, Rh, RhO2, Os, OsO2, Ru, RuO2 Re, ReO3, Pd and Au.
(20) The second thin film includes a thin film made of one or more ferroelectric substances selected from the group consisting of PZT, PLT, PLZT, SBT, PbTiO3, SrTiO3 and BaTiO3.
(21) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a first thin film having one or a plurality of films directly or indirectly over a first major surface of a wafer;
(b) the step of forming a positive type first photoresist film having a square sectional shape at the upper end or upper half of the pattern side face directly or indirectly over the first thin film;
(c) the step of forming a first resist film pattern over the first thin film by exposing the first photoresist film by a reduction projection exposure processing and subsequently by developing the exposed first photoresist film;
(d) the step of forming a gate electrode of a MISFET over the first major surface of the wafer by patterning the first thin film by a dry-etching method using as the mask the first resist film;
(e) the step of forming a second thin film having one or a plurality of films directly or indirectly over the first major surface of the wafer formed with the gate electrode;
(f) the step of forming a positive type second photoresist film having a less square sectional shape than that of the first photoresist film at the upper end or upper half of the pattern side face directly or indirectly by spin-coating over the second thin film;
(g) the step of forming a second resist film pattern over the second thin film by exposing the second photoresist film by a reduction projection exposure processing and subsequently by developing the exposed second photoresist film;
(h) the step of patterning the second thin film by a dry-etching method using as the mask the second resist film so that the side face of the thin film pattern may be normally tapered so as to reach the lower end thereof; and
(i) the step of overetching the thin film pattern, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(22) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a first thin film having one or a plurality of films directly or indirectly over a first major surface of a wafer;
(b) the step of forming a first photoresist film having a square sectional shape at the upper end or upper half of the pattern side face directly or indirectly over the first thin film;
(c) the step of forming a first resist film pattern over the first thin film by exposing the first photoresist film by a reduction projection exposure processing and subsequently by developing the exposed first photoresist film;
(d) the step of forming a gate electrode of a MISFET over the first major surface of the wafer by patterning the first thin film by a dry-etching method using as the mask the first resist film;
(e) the step of forming a second thin film including a conductive film having one or a plurality of films directly or indirectly over the first major surface of the wafer formed with the gate electrode;
(f) the step of forming a second photoresist film having a less square sectional shape than that of the first photoresist film at the upper end or upper half of the pattern side face directly or indirectly over the second thin film;
(g) the step of forming a second resist film pattern over the second thin film by exposing the second photoresist film by a reduction projection exposure processing and subsequently by developing the exposed second photoresist film;
(h) the step of patterning the second thin film by a dry-etching method using as the mask the second resist pattern so that the side face of the thin film pattern may be tapered to macroscopically protrude upward and to reach the lower end thereof; and
(i) the step of overetching the thin film pattern, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(23) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a thin film having one or a plurality of films including a film liable to be deposited on the side wall, directly or indirectly over a first major surface of a wafer;
(b) the step of forming a positive resist film pattern, which has a generally vertical side face of at least its lower half and which is rounded at the outer periphery of its head, directly or indirectly over the thin film;
(c) the step of patterning by a dry-etching method the thin film by using as the mask by the resist film pattern so that the side face of the thin film pattern may be tapered to macroscopically protrude upward and to reach the lower end thereof and so that the side face of the side wall deposited film deposited on the individual side faces of the resist film pattern and the thin film pattern may be tapered to macroscopically protrude upward and to reach the lower ends thereof; and
(d) the step of overetching the thin film pattern, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(24) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a thin film having one or a plurality of films including a film liable to be deposited on the side wall, directly or indirectly over a first major surface of a wafer;
(b) the step of forming a positive resist film pattern having a generally vertical side face directly or indirectly over the thin film;
(c) the step of normally tapering the outer periphery of the head of the resist film pattern by baking the resist film pattern;
(d) the step of patterning by a dry-etching method the thin film by using as the mask the resist film pattern so that the side face of the thin film pattern may be normally tapered so as to reach the lower end thereof and so that the side face of the side wall deposited film deposited on the individual side faces of the resist film pattern and the thin film pattern may be normally tapered so as to reach the lower ends thereof; and
(e) the step of overetching the thin film pattern, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(25) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a thin film having one or a plurality of films including a film liable to be deposited on the side wall, directly or indirectly over a first major surface of a wafer;
(b) the step of forming a photoresist film directly or indirectly by spin-coating over the thin film;
(c) the step of forming a predetermined resist film pattern by exposing and developing the photoresist film;
(d) the step of patterning by a dry-etching method the thin film by using as the mask t he resist film pattern so that the side face of the thin film pattern may be normally tapered so as to reach the lower end thereof; and
(e) the step of overetching the thin film pattern, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern,
wherein the outer periphery of the head of the resist film pattern is either normally tapered or rounded by controlling the focusing condition of the exposing beam at the time of exposing the photoresist film.
(26) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a first thin film having one or a plurality of films directly or indirectly over a first major surface of a wafer;
(b) the step of forming a first photoresist film made of a positive type chemically amplified photoresist directly or indirectly over the first thin film;
(c) the step of forming a first resist film pattern over the first thin film by exposing and developing the first photoresist film;
(d) the step of forming a gate electrode of a MISFET over the first major surface of the wafer by patterning the first thin film by a dry-etching method using as the mask by the first resist film;
(e) the step of forming a second thin film having one or a plurality of films including a film liable to be deposited on the side wall at a dry-etching time directly or indirectly over the first major surface of the wafer formed with the gate electrode;
(f) the step of forming a second photoresist film made of a negative type chemically amplified photoresist directly or indirectly over the second thin film;
(g) the step of forming a second resist film pattern having a rounded outer periphery at its head over the second thin film by exposing and developing the second photoresist film; and
(h) the step of patterning the second thin film by a dry-etching method using as the mask the second resist film.
(27) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a first thin film having one or a plurality of films directly or indirectly over a first major surface of a wafer;
(b) the step of forming a first photoresist film made of a positive type chemically amplified photoresist directly or indirectly over the first thin film;
(c) the step of forming a first resist film pattern over the first thin film by exposing and developing the first photoresist film;
(d) the step of forming a gate electrode of a MISFET over the first major surface of the wafer by patterning the first thin film by a dry-etching method using as the mask the first resist film;
(e) the step of forming a second thin film having one or a plurality of films including a film liable to be deposited on the side wall at a dry-etching time directly or indirectly over the first major surface of the wafer formed with the gate electrode;
(f) the step of forming a second photoresist film made of a positive type chemically amplified photoresist directly or indirectly over the second thin film;
(g) the step of forming a second resist film pattern over the second thin film by exposing and developing the second photoresist film;
(h) the step of melting only the surface of the second resist film pattern by irradiating the second resist film pattern with ultraviolet radiation;
(i) the step of forming a second resist film pattern having a rounded outer periphery at its head by applying an acidic polymer by spin-coating over the surface of the second resist film pattern melted only at its surface and subsequently by baking the second resist film pattern; and
(j) the step of patterning the second thin film by a dry-etching method using as the mask the second resist film.
(28) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a first thin film having one or a plurality of films directly or indirectly over a first major surface of a wafer;
(b) the step of forming a first photoresist film made of a positive type methacrylate photoresist directly or indirectly over the first thin film;
(c) the step of forming a first resist film pattern over the first thin film by exposing and developing the first photoresist film;
(d) the step of forming a gate electrode of a MISFET over the first major surface of the wafer by patterning the first thin film by a dry-etching method using as the mask the first resist film;
(e) the step of forming a second thin film having one or a plurality of films including a film liable to be deposited on the side wall at a dry-etching time directly or indirectly over the first major surface of the wafer formed with the gate electrode;
(f) the step of forming a second photoresist film made of a negative type methacrylate photoresist directly or indirectly by spin-coating over the second thin film;
(g) the step of forming a second resist film pattern having a rounded outer periphery at its head over the second thin film by exposing and developing the second photoresist film; and
(h) the step of patterning the second thin film by a dry-etching method using as the mask the second resist film.
(29) According to the present invention, there is provided a semiconductor integrated circuit device manufacturing process, comprising:
(a) the step of forming a thin film, which has one or a plurality of films including a film liable to be deposited on a side wall, directly or indirectly over a first major surface of a wafer;
(b) the step of forming a positive type photoresist film directly or indirectly by spin-coating over the thin film;
(c) the step of forming a predetermined resist film pattern by exposing and developing the photoresist film;
(d) the step of normally tapering the outer periphery of the head of the resist film pattern, by performing a dry-etching for a short time period under the conditions that only the resist film pattern is substantially etched and the etch-off progresses obliquely from the ridge of the head of the resist film pattern;
(e) the step of patterning the thin film by a dry-etching method using as the mask the resist film pattern; and
(f) the step of overetching the thin film pattern, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.